The present invention relates to systems, such as an asynchronous transfer mode (ATM) network for example, where information is transmitted by means of fixed length cell streams via a slotted transmission medium. It allows on-the-fly processing of cells up to very high data transmission rates.
Cell-processing systems, like communication networks and storage systems, are getting more and more important. An advantage of these kind of cell-based systems is that each and any cell is autonomous and can be routed through a network, for example, just by making use of the information carried in the cell""s header. Asynchronous transfer mode (ATM) data transmission networks are the most well known cell processing systems. The ATM data transmission technology has the potential to revolutionize the way networks are built. This technology enables high-speed data transmission rates and supports many types of traffic including, data, facsimile, voice, real-time video, and images, just to name the most important types encountered in a typical multimedia environment. ATM is suited for local area networks (LAN) as well as wide area networks (WAN) and takes:advantage of the high throughput rates possible on optical fibers.
Typical devices for cell processing systems of any kind are: routers, hubs, switches, e.g. used for interconnection purposes, and adapter cards for linking computers or other devices such as printers, plotters, scanners, disk drives, fax machines, network sniffers, to a cell processing system. The faster the cells are transmitted in such a cell processing system, the more complex and expensive the cell handling and processing gets. The problems encountered if one increases the data transmission rate are elucidated in the following by means of an example.
The higher the data transmission rate in a cell based system (e.g. an ATM system) is, the faster certain operations must be performed on the cells. On-the-fly cell processing which usually requires that all operations are completed within a given number of clock cycles (corresponding to the time until the next cell on the slotted medium arrives) is getting difficult, if not even impossible. The slot duration on the medium defines the maximum duration a process step may take. With increasing data transmission rates, the time until arrival of the next cell gets shorter and shorter. To meet this time, either the number of clock cycles for a given operation must be cut, or the duration of the time cycles must be shortened, i.e. devices must be provided which can be operated at higher clock rates. The first approach is often limited by the kind of operation to be performed, e.g. a binary search of 16000 addresses requires log2(16000)=14 comparisons and hence 14 clock cycles. The second possibility is limited by the chosen technology base which determines the time a logic circuit needs to perform its function. For each known technology base there is an upper processing speed limit defined by the underlying physical effects made use of.
Some cell processing systems have reached data transmission rates where the bounds of possibility are reached already, or will be reached soon. There is a demand for new approaches to circumnavigate or solve this problem. In particular ATM networks operating in the Gigabit per second range have reached a stage where new solutions are needed.
It is thus an object of the present invention to provide a new concept for fixed length cell processing even at very high data transmission rates.
It is a further object of the present invention to provide an apparatus and method enabling very fast on-the-fly processing of fixed length cells.
It is another object of the present invention to apply the inventive approach to asynchronous transfer mode systems.
The invention as claimed is intended to meet these objectives. According to the present invention, the consecutive fixed length cells on a slotted medium are assigned to N parallel, identical processing paths each of which comprise one or more processing units. Due to this, the number of clock cycles available to such a Processing unit is multiplied by N if only each (N+1)-th cell is processed by the same processing path. This introduces N virtual but identical data processing paths.